NF=00, SMBS=0, RDRFS=0, ACKBT=0, ACKWP=0, ACKBR=0, WAIT=0
I2C Bus Mode Register 3
| NF | Noise Filter Stage Selection 0 (00): Noise of up to one fIIC cycle is filtered out (single-stage filter). 1 (01): Noise of up to two fIIC cycles is filtered out (2-stage filter). 2 (10): Noise of up to three fIIC cycles is filtered out (3-stage filter). 3 (11): Noise of up to four fIIC cycles is filtered out (4-stage filter) |
| ACKBR | Receive Acknowledge 0 (0): A 0 is received as the acknowledge bit (ACK reception). 1 (1): A 1 is received as the acknowledge bit (NACK reception). |
| ACKBT | Transmit Acknowledge 0 (0): A 0 is sent as the acknowledge bit (ACK transmission). 1 (1): A 1 is sent as the acknowledge bit (NACK transmission). |
| ACKWP | ACKBT Write Protect 0 (0): Modification of the ACKBT bit is disabled. 1 (1): Modification of the ACKBT bit is enabled. |
| RDRFS | RDRF Flag Set Timing Selection 0 (0): The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) 1 (1): The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) |
| WAIT | WAIT Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 0 (0): No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) 1 (1): WAIT (The period between ninth clock cycle and first clock cycle is held low.) |
| SMBS | SMBus/I2C Bus Selection 0 (0): The I2C bus is selected. 1 (1): The SMBus is selected. |